The present invention relates to an active driver for generating an internal voltage; and, more particularly, to an active driver for generating an internal voltage having a stable potential level during a test operation.
In dynamic random access memory (DRAM), peripheral circuits, memory arrays and the like taking an internal voltage have a difficulty in doing a stable operation due to serious load variations for each operation mode. Because of this, in case of core voltage VCORE used for operating cells, a sub word line driver, a sense amplifier, an X-decoder and a Y-decoder in DRAM, a standby driver or an active driver is selectively used depending on an operation mode.
FIG. 1 is a block diagram showing a conventional device for generating a core voltage VCORE.
Referring to FIG. 1, the conventional device for generating a core voltage VCORE is provided with a reference voltage VREF generator 10 for taking an external voltage VDD and a ground voltage VSS and generating a reference voltage VREF, a core voltage VCORE standby driver 20 that operates when a memory is in a precharge state and generates a core voltage VCORE based on the reference voltage VREF, and a core voltage VCORE active driver 30 that operates when the memory is in an active state and produces the core voltage VCORE from the reference voltage VREF.
More specifically, the core voltage active driver 30 operates in response to an active signal ACT.
Here, an activation operation of the active signal ACT means a sensing operation being conducted under a state that a word line of DRAM has been enabled. This implies that much current is consumed in a sense amplifier by the sensing operation. That is, since the potential level of the core voltage VCORE can drop, the core voltage active driver 30 using a transistor with large capacity should be operated.
Similarly, the core voltage standby driver 20 operates in response to a precharge signal PRECHARGE.
Here, an activation operation of the precharge signal PRECHARGE means a precharge operation of DRAM, which does not use much current. Thus, the core voltage standby driver 20 using a transistor with small capacity should be utilized to prevent unnecessary current consumption.
FIG. 2 is a detailed circuit diagram of the core voltage active driver 30 shown in FIG. 1.
Referring to FIG. 2, the core voltage active driver 30 is provided with a comparator that generates the core voltage VCORE when the active signal ACT is activated to a logic high level and the reference voltage VREF is inputted.
That is, when the active signal ACT is activated to a logic high level, PMOS transistors P2, P5 and P7 are turned off and NMOS transistors N3 and N7 are turned on and thus the core voltage active driver 30 starts to operate.
When the core voltage active driver 30 starts to operate, it operates in two types of states depending on a potential level of a half core voltage HALF_VCORE.
Here, the half core voltage HALF_VCORE denotes a voltage that is obtained by dividing the core voltage VCORE outputted from the cover voltage active driver 30 with resistance values of resistive elements PD1 and PD2. If the elements PD1 and PD2 have the same resistance value, they have a potential level that is derived by dividing the potential level of the core voltage VCORE by 2.
The following is a description for a case where the core voltage active driver 30 is in an initial state and the potential level of the half core voltage HALF_VCORE is lower than a potential level of the reference voltage VREF. Of course, it is assumed that the potential level of the half core voltage HALF_VCORE is higher than a threshold voltage Vt of an NMOS transistor N4. In addition, it is further assumed that N2 and N4 that are two input ends of the comparator and NMOS transistors are the same sized-transistors.
Since the potential level of the half core voltage HALF_VCORE is lower than the potential level of the reference voltage VREF, the gate-source voltage VGS of the NMOS transistor N2 has a potential level higher than that of the NMOS transistor N4. That is, the voltage drop arising at a node L is larger than that at a node R. The voltage drop at the node L causes the PMOS transistor P1 to be turned on and the external voltage VDD supplied through the PMOS transistor P1 causes the NMOS transistor N5 to be turned on. Likewise, the voltage drop at the node R causes the PMOS transistor P6 to be turned on, but it is turned on less than the NMOS transistor N5 turned on by the voltage drop at the node L. Therefore, the charge supply capability of the PMOS transistor P6 is smaller than that of the NMOS transistor N5.
A driving node DRV becomes a logic low level due to the operation set forth above, and thus, a PMOS transistor P8 is turned on to elevate the potential level of the core voltage VCORE. The core voltage VCORE with potential level being so elevated is continuously kept until the potential level of the half core voltage HALF_VCORE becomes higher than that of the reference voltage VREF.
The following is a description for a case where the potential level of the half core voltage HALF_VCORE is higher than that of the reference voltage VREF.
Since the potential level of the half core voltage HALF_VCORE is higher than that of the reference voltage VREF, the gate-source voltage VGS of the NMOS transistor N2 has a potential level lower than that of the NMOS transistor N4. That is, the voltage drop arising at the node L is less than that at the node R. The voltage drop at the node R causes the PMOS transistor P6 to be turned on. Similarly, the voltage drop at the node L causes the PMOS transistor P1 to be turned on and the external voltage VDD supplied through the PMOS transistor P1 causes the NMOS transistor N5 to be turned on, but it is turned on less than the PMOS transistor P6 turned on by the voltage drop at the node R. Therefore, the charge supply capability of the NMOS transistor N5 is smaller than that of the PMOS transistor P6.
The driving node DRV becomes a logic high level due to the operation described above, and thus, the PMOS transistor P8 is turned off, which does not supply the external voltage VDD to the output end of the core voltage active driver 30. The operation set forth above is continued until the potential level of the half core voltage HALF_VCORE becomes lower than that of the reference voltage VREF.
In the prior art, the sole difference between the core voltage standby driver 20 and the core voltage active driver 30 is that the sizes of transistors used therein are different from each other. Therefore, the operation of the core voltage standby driver 20 is the same as that of the core voltage active driver 30 mentioned above.
In case DRAM operates in normal mode, the core voltage VCORE can be maximally consumed in the following case.
Under the circumstance that the word lines of all memory banks are active, plural bit lines are enabled at time intervals of tCCD (column address to column address delay) in an alternate manner for each memory bank, followed by write operation.
In other words, it is designed in a manner that the driving capability of the core voltage active driver 30 is based on the circumstances set forth above.
However, in the process of manufacturing DRAM, since test time of DRAM highly affects its cost, it is being progressed in direction of minimizing the test time.
That is, if DRAM operates in test mode, the core voltage VCORE is maximally consumed in the following case. Specifically, much more core voltage VCORE is consumed compared with the case of being most consumed if DRAM operates in normal mode.
If DRAM operates in test mode, under the circumstance that the word lines of all memory banks are active, plural bit lines are enabled at time intervals of tCCD in an alternate manner for each memory bank, followed by write operation.
In this case, the driving capability of the conventional core voltage active driver 30 is limited to supplying the core voltage VCORE required for test operation.
As such, if the amount of consumption of the core voltage VCORE is greater than the driving capability of the core voltage active driver 30, there occurs a case where the potential level of the core voltage VCORE is not constantly maintained, which may cause a malfunctioning of memory device.
Further, the reliability of test operation of DRAM much lower, thereby increasing manufacturing cost.